Non-volatile memories are commonly used in several applications when the data stored in the memory need to be preserved even when the power supply is off. Within the class of non-volatile memories, the electrically programmable (and erasable) memories, such as flash memories, have become very popular in applications in which the data to be stored are not immutable (as it might be, e.g., the case of a consolidated code for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored.
Referring to FIG. 1, a non-volatile memory 100, including for example an E2PROM, particularly of flash type, is schematically illustrated. The flash memory 100 is integrated on a chip of semiconductor material and includes a memory matrix 105 of memory cells MC, typically including floating gate MOS transistors. In the memory matrix 105, the memory cells MC are arranged in a plurality of rows and a plurality of columns, for example, with a NOR architecture.
Each row is controlled by a respective word line WL, a control gate terminal of the corresponding memory cells MC being connected thereto, and each column is controlled by a respective bit line BL, a drain terminal of the corresponding memory cells MC being connected thereto; a source terminal of the memory cells MC is connected to a reference voltage supply line providing a reference voltage or ground. In this way, each memory cell MC can be addressed by selecting a corresponding word line/bit line pair.
Word-line selector circuits 110 and bit-line selector circuits 115 are provided; these circuits, known per-se and therefore merely schematized as blocks in the drawings, perform the selection of the word lines WL and of the bit lines BL on the basis of a word-line address binary code WLADD and a bit-line address binary code BLADD, respectively, which are part of a memory address binary code ADD, for example received by the flash memory 100 from an external device (such as a microprocessor) on the occasion of an access to the memory. For example, during a reading operation on the flash memory 100, the word-line selector circuits 110 decode the word-line address code WLADD and select a corresponding one of the word lines WL; the bit-line selector circuits 115 decode the bit-line address code BLADD and typically select a corresponding packet of (e.g., eight or sixteen) bit lines BL.
The word-line selector circuits 110 and the bit-line selector circuits 115 interface with read/write circuits, including all the components which are normally required for reading logic values currently stored in the selected memory cells MC, and for writing desired new logic values thereinto. Particularly, the read/write circuits include voltage generators and boosters 118, such as charge pumps, and a plurality of sense amplifiers 120 (for the sake of clarity only one of those shown in the drawing—the number of sense amplifiers generally depends on the read parallelism, i.e., on the number of bit lines in the selected packets).
The voltage generators and boosters 118 provide a boosted voltage Vpp and a reference supply voltage Vref (for example, the ground) starting from the supply voltage Vdd to the word-line and bit-line selector circuits 110 and 115.
The operation of the flash memory 100 is controlled by a control unit 125, which outputs a plurality of control signals, denoted as a whole with Sc, to be provided to corresponding circuital blocks of the flash memory 100.
The sense amplifier 120 shown in FIG. 1 has an input terminal coupled to the output of the bit line selector circuits 115 for sensing a current Ic sunk by a selected memory cell MC, a current value corresponding to a logic value stored in the memory cell MC.
In the case of a two-level flash memory, the memory cells MC have two possible states, a programmed state, corresponding by convention to a low logic value ‘0’, and a non-programmed, or erased, state, corresponding to a high logic value ‘1’; these two states are respectively associated, still by convention, with a first, higher value, and a second, lower value of the threshold voltage of the memory cells MC. Thus, a bit of information can be written into a memory cell MC and the current Ic sunk by a selected memory cell MC, when properly biased, corresponds to the stored logic value. Increasing threshold voltages correspond to decreasing memory cell currents Ic and, then, a value of the memory cell current Ic‘1’, corresponding to the high logic value ‘1’, is greater than a value of the memory cell current Ic‘0’, corresponding to the low logic value ‘0’.
In a multi-level flash memory 100, each memory cell MC may be programmed to multiple levels, each one associated with a corresponding range of the threshold voltage of the cells; each programming level represents a different logic value. Typically (but not necessarily), a number L of levels is a power of 2; therefore, a memory cell MC with L=2B levels stores a logic value consisting of B bits of information.
The memory cell MC can be programmed by applying a high (positive) voltage pulse to the control gate terminal, i.e., to the respective word line WL, and to the drain terminal, i.e., to the respective bit line BL, with respect to the source terminal and to a semiconductor well of the chip in which it is integrated (which well can be biased at a negative voltage with respect to the source terminal). The so-applied voltages supply sufficient energy to some electrons (so-called “hot”) flowing through a channel of the floating gate transistor to cause them to be injected into the floating gate. The charge transferred into the floating gate increases the threshold voltage of the cell, and it is retained for any practical time period.
A programmed memory cell MC can be erased by removing electrons from its floating gate; particularly, a high (negative) voltage pulse can be applied to the control gate terminal, i.e., to the respective word line WL, with respect to the source terminal and the semiconductor well of the chip in which it is integrated (while the drain terminal, i.e., the respective bit line BL, can be left floating). This voltage generates a Fowler-Nordheim current by quantum-mechanical tunneling, current flowing between the floating gate and the well and the source terminal, and which removes the charge from the floating gate.
The flash memory 100 further includes an alignment 130 of a number of reference cells RCr, RCp, RCe, RCd structurally identical to the memory cells MC. The sense amplifier 120 has a reference input terminal selectively coupable to a reference cell RCr, RCp, RCe, RCd of the alignment 130 that, when connected to the sense amplifier 120 (and properly biased), provides a reference current Ir to be compared with the current Ic to be sensed, so as to discriminate the logic value stored in the selected memory cell MC, or to verify a correct programming or erase (not too high, not too low) level of the considered memory cell MC.
An output terminal of the sense amplifier 120 provides an output signal DATA taking a high or low logic value in accordance with the programming state of the selected memory cell MC.
The flash memory 100 can include a plurality of alignments 130 of reference cells RCr, RCp, RCe, RCd (only one of those is shown in FIG. 1 for simplicity of illustration), exploited during reading or verify operations on the memory cells MC. Typically, the number of the reference cells RCr, RCp, RCe, RCd depends on the storage capability and on the architecture of the flash memory 100 and on the fact that the flash memory 100 is multi-level.
In an exemplificative way the reference cells RCr, RCp, RCe, RCd are kept conductive by applying a respective proper biasing voltage Vr, Vpv, Vev, Vdv, which depends on the operation to be performed (read, program verify, erase verify, depletion verify) on the cells MC, at the control gate terminal thereof, while the source terminal is maintained at ground.
Switches SWr, SWp, SWe, SWd have each a first terminal connected to a drain terminal of a respective one of the reference cells RCr, RCp, RCe and RCd, and a second terminal connected to the reference terminal of the sense amplifier 120. Each of the switches SWr, SWp, SWe, SWd is controlled by a respective control signal READ, PRG, ERASE, DPL provided by the control unit 125 so that the corresponding reference cell RCr, RCp, RCe, RCd sinks a reference current Ir only when it is connected to the sense amplifier 120, the reference current Ir depending on the programming state of the reference cell RCr, RCp, RCe, RCd.
Each reference cell RCr, RCp, RCe, RCd is exploited in a respective operation to be performed on the selected memory cells MC. Particularly, during a post-manufacture testing phase of the memory device a specific task (read, program verify, erase verify, depletion verify) is assigned to each reference cell RCr, RCp, RCe, RCd that, accordingly, is programmed in such a way to have a suitable threshold voltage specific for that task.
For example, a read reference cell RCr is exploited during reading operations on the memory matrix 105 for discriminating the logic value stored in a memory cell MC selected for the reading thereof. During the reading operation the control unit 125 asserts a read control signal READ, so as to connect the read reference cell RCr to the sense amplifier 120. The read reference cell RCr is programmed at a read threshold voltage such that a value of the reference current Ir sunk by it (when properly biased) is, for example, intermediate between the value of the high memory cell current Ic‘1’ and the low memory cell current Ic‘0’.
A program verify reference cell RCp is exploited during program-verify operations on the memory matrix 105, e.g., for verifying the completion of a program operation on a selected memory cell MC. During a program-verify operation the control unit 125 asserts a program verify control signal PRG so as to connect the program verify reference cell RCp to the sense amplifier 120. The program verify reference cell RCp is programmed at a level corresponding to the low logic value ‘0’ and, accordingly, has a program-verify threshold voltage typically higher than the read threshold voltage (in order to assure that the cells are programmed with a suitable margin).
An erase verify reference cell RCe is exploited during erase-verify operations on the memory matrix 105 for verifying the completion of an erase operation on selected memory cells MC. During an erase-verify operation the control unit 125 asserts an erase verify control signal ERASE, so as to connect the erase verify reference cell RCe to the sense amplifier 120. The erase verify reference cell RCe is programmed at the level corresponding to the high logic value ‘1’ and, accordingly, has an erase-verify threshold voltage lower than the read threshold voltage (in order to assure that the cells are erased with a suitable margin).
A depletion verify reference cell RCd is exploited during depletion-verify operations on the memory matrix 105, for verifying that, after an erase operation, the threshold voltage of selected memory cells MC has not reached a value excessively low or even negative. During a depletion-verify operation the control unit 125 asserts a depletion verify control signal DPL, so as to connect the depletion verify reference cell RCd to the sense amplifier 120. The depletion verify reference cell RCd is programmed at a level corresponding to the high logic value ‘1’ and a depletion-verify threshold voltage thereof corresponds to an inferior limit of the threshold voltage acceptable for the memory cells MC, accordingly lower than the erase-verify threshold voltage.
In the case the flash memory 100 is multi-level, the reference cells RCr, RCp exploited during a reading or verify operation on the memory cell MC are typically in a number greater than one. For example, in a four-level flash memory 100 during a reading operation up to three read reference cells RCr may be necessary, for being able to discriminate the four programming states of the memory cells MC; as many reference cells (programmed at voltage levels slightly higher than those of the read reference cells) are necessary for the program verify.
During the post-manufacture testing phase of the memory devices all the reference cells RCr, RCp, RCe, RCd are programmed at the desired level by a programming/erasing procedure requiring a relatively long time, typically of the order of seconds. In fact, each reference cell RCr, RCp, RCe, RCd has to reach the desired threshold voltage with a relatively high accuracy, especially in the case of a multi-level flash memory 100, in which each threshold voltage range corresponds to a different logic value, and the difference between the different threshold voltage values is rather small. For each reference cell RCr, RCp, RCe, RCd a program-verify sequence and an erase-verify sequence are typically repeated several times until the desired threshold voltage is reached with the required accuracy, because the programming/erasing procedure is very sensitive to process variations, which affect the gate oxide thickness, the inter-poly dielectric thickness, the active area width, the gate length and the like, and which have a strong impact on the programming efficiency. Accordingly, the relatively long time required for correctly setting the reference cells in the testing phase of the memory may substantially increase the cost of the flash memory 100.
Quite similar problems are found in the case of other types of non-volatile semiconductor memories, such as the phase-change memories (also known as “Ovonics Universal Memories” or OUM), in which the resistance variation caused by the phase change (from crystalline to amorphous) of suitable materials is exploited for storing information.